ULTRACOMP: ROBUST COMPARATOR TOPOLOGY FOR LOWPOWER HIGH-ACCURACY COMPUTING

Abstract

As modern electronic systems demand both energy efficiency and precision, comparator design has become a critical focus in low-power applications such as portable devices, biomedical instrumentation, and IoT systems. This study presents DyNoComp, a novel noise-aware threestage comparator topology engineered to deliver high accuracy while minimizing power consumption. By integrating noise reduction techniques into the multi-stage architecture, the proposed design mitigates offset variations, enhances decision reliability, and ensures stable operation under low supply voltages. Simulation results demonstrate that DyNoComp achieves significant improvements in noise immunity, speed, and power efficiency compared to conventional comparator designs. The architecture’s scalability and robustness make it well-suited for next-generation low-power integrated circuits where precision and energy savings are paramount. This work underscores the potential of noise-aware design methodologies in advancing efficient and reliable comparator architectures for emerging electronic applications.